1. Field of the Invention
The invention relates generally to a manufacturing process for a vacuum microelectronics device and more particularly to a method for fabricating a field emission device (FED) having a uniform silicon tip as an emitter and a submicron-scale gate aperture which can reduce the operating voltage of the device.
2. Description of the Related Art
Ever since C. A. Spindt set forth a description of a micrometer-scale gated field emission device (FED) in 1969, such devices have been conventional in the field of vacuum microelectronics. Until now, there have been two predominant methods for fabricating the field emission device. One of these methods uses the metal evaporation technique similar to Spindt's, and the other makes use of the current IC (integrated circuits) fabrication process, especially silicon-based ICs. There are, however, at least two deficiencies encountered with Spindt's method. First, it is difficult to control the uniformity of a plurality of emission tips formed over a large area, e.g., an array of field emission devices, with metal evaporation techniques. Second, extra equipment, such as an oblique-angle evaporator or a substrate-holder spinner, must be bought because such devices are not involved in the standard CMOS process. Moreover, these devices complicate the process flow and limit the formation of silicon tip arrays over a large area. By comparison, the second method of utilizing the IC fabrication process simplifies the process steps.
The above methods for fabricating field emission arrays have been further classified into two rough categories: the self-aligned and the non-self-aligned methods. Since the operating voltage of a field emission device is proportional to the spacing between a gate and an emitter tip, this operating voltage can be lowered by decreasing the distance between the gate and the tip. To lower the operating voltage, the width of the gate aperture is typically decreased to approach the emitter tip as closely as possible without making contact. In addition, it is critical that the emitter tip is aligned symmetrically within the center portion of the gate aperture to reduce the leakage current induced therefrom. The non-self-aligned method, however, cannot meet the above requirements, and therefore is inferior to the self-aligned method. The self-aligned method typically meets these requirements by employing a lift-off technique.
FIGS. 1A-1E illustrate the process steps of a conventional lift-off technique for fabricating a field-emission device. As shown in FIG. 1A, an oxide or nitride layer (not shown) is formed over a silicon substrate 1, such as single crystalline silicon, polysilicon or amorphous silicon, by thermal oxidation or deposition. Through application of the lithography technique, the oxide or nitride layer is then patterned into a capping layer 10 for defining the position of an emitter.
Referring to FIG. 1B, the surface of the silicon substrate 1 is masked with capping layer 10 and etched into a silicon cone 12, projecting over the silicon substrate 1, by means of wet etching or isotropic dry etching. The top region of the silicon cone 12 adjacent to the capping layer 10 is typically about 1000 .ANG. in width.
As shown in FIG. 1C, thermal oxidation is then applied to the silicon substrate 1 and the side walls of the silicon cone 12 to form an oxide layer 14. Simultaneously, the thermal oxidation consumes a portion of the silicon material, thereby sharpening the silicon cone 12 into a silicon tip 16. To ensure that the silicon cone 12 is sharpened and not completely removed, the oxide layer 14 typically will not exceed 800 .ANG. in thickness.
Referring to FIG. 1D, a dielectric layer 100, such as silicon oxide, and a metal layer 18 are subsequently deposited over the capping layer 10 and the oxide layer 14, respectively, by perpendicular direction physical vapor deposition (PVD), such as E-Gun evaporation. Capping layer 10 serves to mask the portion of oxide layer 14 directly over silicon cone 16. Finally, diluted hydrofluoric acid is employed to etch a portion of the oxide layer 14 disposed on the side walls of the silicon tip 16, as shown in FIG. 1E. The acid also lifts off the portions of capping layer 10 accompanying the dielectric layer 100 and the metal layer 18 thereon to expose silicon tip 16 as an emitter. The remaining metal layer 18 serves as a gate and the gate aperture 19 defines the spacing between the emitter and the gate.
The above described conventional fabrication process has a number of drawbacks. First, the dimensions of the gate aperture 19 are limited by the size of the capping layer 10 (see FIG. 1D). Second, the dielectric layer 100 cannot withstand high voltage because it has been formed by E-Gun evaporation. Third, the thickness of the dielectric layer 100 typically determines the relative geometric position between the emitter and the gate, thereby having a large effect on the electrical characteristics of the field emission device. The E-Gun evaporation process, however, does not provide sufficient control to accurately fabricate a uniform dielectric layer 100. Over a larger area, this non-uniform dielectric layer typically produces divergent device characteristics, which is an undesired attribute for a field emission device.